Clock gating is an effective technique for minimizing dynamic power in sequential circuits. Applying clock-gating at gate-level not only saves time compared to implementing clock-gating in the RTL code but also saves power and can easily be automated in the synthesis process. This paper presents simulation results on various types of clock-gating at different hierarchical levels on a Serial Peripheral Interface (SPI) design. In general power savings of about 30% and 36% reduction on toggle rate can be seen with different complex clockgating methods with respect to no clock-gating in the design.

Due to the power limitation in wireless sensor nodes, special attention is required in optimizing the power consumption of the necessary electronics on a node. This can be done at different levels of abstraction, While architectural level optimization brings a major power reduction due to the fact that any changes made at this level of abstraction will be reflected back to the lower levels, all other levels must be also considered in an overall power reduction strategy. This paper discusses different possibilities of power reduction at system, architectural, and circuit level of the node's electronics. It also addresses different communication protocols and their effect on the power consumption of a wireless sensor node.