The paper addresses the ongoing research on verication and simulation of real-time systems at SEPC 1 . The approach taken is an engineering approach dedicated t o t o ol development aiming at a wider dissemination of formal methods and techniques in industrial application. The tool-environment under construction TVS, is dedicated to formal veri cation and simulation of real-time systems. TVS comprises language front-ends for both speci cation-and implementation languages, a veri cation notation XTG and a simulation language SL. XTG is a new formalism for describing real-time systems. It is an engineering notation based o n t i m e d automata aimed a t p r oviding a simple representation for high-level speci cation languages. By translating a high level speci cation into an XTG system, a representation is obtained t h a t better suits the application of automatic veri cation and simulation techniques. XTG is suited a s c oncrete representation for languages that allow extensive modeling of data, have a maximal progress semantics, and model interprocess-communication by valuepassing through data channels.