No abstract

-A new scheme is presented for generating optimal timing and power models, which can speed up timing and power analyses with full accuracy in systemon-chip (SoC) designs. In this scheme, the nonlinear multidimensional timing and power lookup tables in semiconductor libraries are transformed into optimized (piecewise) polynomial equations in an efficient and accurate manner. The transform problem is mathematically defined as a least square problem, which is efficiently solved by a set of robust numerical algorithms. These optimized polynomial equations are then represented using the delay and power calculation language (DPCL), which can be complied into object code and used by various EDA tools.

Using certificate of generic boolean function, a technology mapper and several other applications are introduced. For multiplexor-based FPGAs, this technology mapper has the same quality as MIS-PGA[6] in terms of area while running faster and having the advantage of being independent of module functionality. Other applications include library function generation, routing cost minimization and peephole logic optimization.

No abstract