t ch = 10 nm L g t ins Drain t ins = 4 nm Ti Pt InGaAs InAlAs InAlAsAbstract: High-mobility III-V transistors are poised to take the lead on future high performance logic operation. If this happens, indium-rich In x Ga 1-x As is the most promising n-channel material. Indeed, remarkable progress has been made, including III-V gate-stacks with ALD-grown gate dielectrics. This paper reviews the evolution of highperformance III-V devices for future logic applications and discuss a possible path forward to further improve their logic figure-of-merits. Introduction:In early 2000s, indium-rich In x Ga 1-x As (x>0.53) has recently emerged as the most promising non-Si n-channel material for post Si CMOS logic applications [1]. This is thanks to the outstanding electron transport characteristics, excellent interfacial quality of the highk/InGaAs gate stack by ALD and co-integration of InGaAsbased heterostructures with Si [1-2]. Recently, significant progress has been made on a variety of GaAs and InGaAs MOSFETs by many different groups. This paper reviews high-performance III-V devices for future logic applications, covers recent advances in some of the key enabling technology of InGaAs MOSFETs, and finally discusses options to further improve the performance of InGaAs MOSFETs.How good are III-V's for future logic applications?: As a way to assess the prospects for a future III-V MOSFET technology with gate lengths in the sub-10 nm range, we started our research in 2005 on state-of-the-art III-V High-Electron-Mobility-Transistors (HEMTs). The HEMT in itself a device with near THz capabilities, was an excellent prototype Field-Effect-Transistor (FET) for future logic. The

This paper reports tri-gate sub-100 nm In 0.53 Ga 0.47 As QW MOSFETs with electrostatic immunity of S = 77 mV/dec., DIBL = 10 mV/V, together with excellent carrier transport of g m,max > 1.5 mS/µm, at V DS = 0.5 V. This result is the best balance of g m,max and S in any reported III-V MOSFETs. In addition, extracted compact model parameter including (μ 0 = 760 cm 2 /V-s and peak v x0 = 1.6×10 7 cm/s) indicate that InGaAs Tri-Gate MOSFETs would be a viable pathway to sub-10nm technology node.Introduction: Indium-rich InGaAs channel materials are a candidate for future low-power logic applications [1-2]. Tri-gate transistor architecture has been successfully demonstrated for improved electrostatics in Si MOSFETs [3][4] and most recently in III-V MOSFETs [5][6]. However, most of III-V tri-gate devices reported so far have shown wide fin geometry or poor interface quality between high-k dielectric and sidewall of etched Fin, failing to demonstrate performance and electrostatics benefit over the best ultrathin-body (UTB) planar III-V QW MOSFETs [7][8]. In this work, tri-gate In 0.53 Ga 0.47 As QW MOSFETs with bi-layer high-k dielectrics of Al 2 O 3 /HfO 2 are reported. In particular, L g = 60 nm tri-gate In 0.53 Ga 0.47 As QW MOSFETs with narrow fin width (W fin ) of 30 nm, fin height (H fin ) of 20 nm and EOT < 1 nm, yield excellent electrostatic integrity and performance benefit over UTB planar III-V MOSFETs, such as S = 77 mV/dec., DIBL = 10 mV/V, g m > 1.5 mS/µm and v ox = 1.6ⅹ10 7 cm/s. This result is significant because it shows that excellent electrostatics and performance can be achieved with high-k oxides directly on an etched tri-gate MOSFETs down to L g = 60 nm.