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As 3D packaging technologies are becoming more and more present in packaging roadmap, applications with higher requirement are rising continuously.Today, one of the main applications requiring 3D technologies is dedicated to nomadic components, including mobile phones, due to their very high compacity and integration capabilities. Those components need to work at high frequency, typically up to 1 GHz. For these frequencies, the resistance and the capacitance of the interconnections have to be minimized, in order to decrease the signal delay. This is a real challenge for 3D integration and especially for post process through silicon vias.In the first part of the paper, a study and a simple model to determine the main parameters responsible for resistance and parasitic capacitance variation will be presented. Then, a technical focus will be done on the improvement of the TSV electrical performances, especially the decreasing of the TSV parasitic capacitance from 2.41 pF to 0.76 pF based on Plasma Enhanced Chemical Vapour Deposition (PECVD) process development. Finally, the integration of this new material on a technological test vehicle with electrical results will be presented and discussed.