The chemical and electrical characteristics were measured of loo-keV Si+ -implanted GaAs at doses of(6-10) X 10 12 cm-2 after rapid thermal annealing (RTA) for times of 5-40 s at temperatures between 850 and 975°C. Optimal conditions were 5 s at 930°C in either Ar or Ar-H2 atmospheres. Purity of the gas ambient was critical at the higher temperatures. Surface degradation was minimal for face-to-face annealing, as compared to exposed Si0 2 encapsulated surfaces. Essentially identical electrical characteristics were obtained by the preferred RTA conditions as compared to 30-min conventional furnace annealing under optimum conditions at 850°C using the controlled atmosphere technique. The markedly different RTA annealing times with comparable electrical characteristics are attributed to the differences in the host lattice damage recovery resulting from heat transfer and the actual duration to reach the desired anneal temperature.

Optimization and the advantages of rapid thermal annealing (RTA) for the electrical activation of deep 300 keV Si+ implants into GaAs are investigated and established for doses of 6 to 8×1012 cm−2. These implant conditions are appropriate for power FETs. Results are compared with those based on conventional controlled atmosphere capless furnace annealing (CAT).The RTA yielded higher peak electron concentrations, high mobilities and greater uniformities in the gateless FET saturation currents. The deep implant results ontrast with those for shallower implants for low noise FETs. These differences are explained using a well-known implant damage model.