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System-on-a-chip architectures are generating increased interest as the level of integration is expanded by the arrival of 0.25pm processes. Many merged D M and logic applications use custom logic circuits that either surround or are embedded in a DRAM core [l, 2,3]. Amore classic ASIC library approach where a D M macro family is used as a logic building block with the software tools associated with ASIC logic macros: i.e., timing analysis, place-and-route, logic simulation, and test generation. The macro operation is generic, yet versatile, allowing gate-array or standard-cell interface personalization. The design has a wide databit interface of 128 or 256 bits, separate databit-in and databit-out to ease bus contention, bit-write capability for multiplexing to narrower databit widths or partial databit-writes, and granulardensity options from 0.5Mb-8Mb. Built-in self test (BIST) with two-dimensional redundancy calculation and allocation, along with in-situ burn-in capability, is also included. The DRAM macro design is architected for reuse on future DRAM-generation subarrays and is adaptable to any number of address or databit-pin configurations. Its methodology and functionality have been verified in a 0.45pm trench DRAM technology.The macro architecture uses 16Mb DRANI attributes; Figure 1 shows a block diagram of the embedded DRAM [3]. It is constructed from basic building blocks where the instances of the subarray is easily replicated to create a macro with a minimum 0.5Mb density and an incremental granularity up to the maximum 8Mb density. A digital secondary sense amplifier in the middle of the subarray is used in conjunction with the low-order addresses to allow wordline-data paging. On a given fetch, 260 internal databits are selected from the array and presented by the digital secondary sense system to the databit-redundancy steering block. This circuitry, on a subarray-by-subarray basis, selects 256 databits for transfer to the databit-out ports. Word redundancy is implemented in each subarray in the classic DRAM fashion. The basic macro inputs and outputs and their definition are given in Table 1. Figures 2 and 3 illustrate the operational timings for a read and write cycle, respectively.The test function is tightly designed into the macro array architecture. BIST is important because it allows large embeddedmemory testing on logic testers without the added die area and performance testing inaccuracies incurred with isolation multiplexers to attach the memory to external pads 141. The majority of memory-array BIST are for SRANIs and are state-machine based. This built-in self test is processor-based and runs from internal microcode or from microcode loaded into boundary scan latches. The BIST logic is implemented as a level-sensitive scan design. This methodology allows full stuck-fault functional test, and diagnosability of the logic before the built-in-self-test evaluates the DRAM and calculates fixability 151. The testing is totally contained on a low-cost logic test system and the DRAM is fully ...

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