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A compact model for early electromigration failures in copper dual-damascene interconnects is proposed. The model is based on the combination of a complete void nucleation model together with a simple mechanism of slit void growth under the via. It is demonstrated that the early electromigration lifetime is well described by a simple analytical expression, from where a statistical distribution can be conveniently obtained. Furthermore, it is shown that the simulation results provide a reasonable estimation for the lifetimes.

Electromigration induced failure development in a copper dual-damascene structure with a through silicon via (TSV) located at the cathode end of the line is studied. The resistance change caused by void growth under the TSV and the interconnect lifetime estimation are modeled based on analytical expressions and also investigated with the help of numerical simulations of fully three-dimensional structures. It is shown that, in addition to the high resistance increase caused by a large void, a small void under the TSV can also lead to a significant resistance increase, particularly in the presence of imperfections at the TSV bottom introduced during the fabrication process. As a consequence, electromigration failure in such structures is likely to have bimodal characteristics. The simulation results have indicated that both modes are important to be considered in order to obtain a more precise description of the interconnect lifetime distribution.