Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) level. I. I The growing economic and social impact of mobile telecommunication devices, together with the evolution of protocols and interoperability requirements among different standards for voice and data, is currently driving

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St Paul, MNAN OPERATING MODULE of a new memory system -a Block-Oriented Random-Access Memory (BORAM)' utilizing nonvolatile semiconductor MNOS' information storage -has been developed*. A fully populated 295K-bit module, it is organized in 32 blocks of 256 words, each word being 36 bits wide. The major performance parameters of this system are its data transfer rate of one word per 150 ns block access time of 2 ps, block read cycle time of 42 /.IS, and write cycle time of 2 ms. The heart of this module is a 2048-bit MNOS-LSI memory chip designed from the beginning to meet the system requirements.The MNOS-BORAM chip has been fabricated by a simple extension of a typical P-channel MOS process. Isolation between MNOS memory transistor array and peripheral circuitry was achieved by a P-diffused wall through an N-type epitaxial layer on a P-type substrate. Another diffusion is added to provide N+ contacts to the isolated N region. The memory transistor has a stepped-gate structure, resulting in €ixed threshold devices that have both a thick oxide layer and a nitride layer for their gate dielectric. Since each gate type requires a separate masking step, there are eight masking steps necessary to manufacture this chip. Only the normal single layer metalization of aluminum is used. The layout rules are relatively generous, with an average of 0.4 mil of minimum widths and spacings in use. In the design approach, essentially static (resistance ratio) logic is the rule. This requires meticulous care to meet performance requirements in spite of the size of the chip (198 x 186 mils').The memory chip (Figure 1 ) is essentially an EAROM organized in 32 randomly addressable blocks, each having 64 serially accessed bits which represent the same bit of 64 different words. The circuit elements providing the access are two 32-bit two-phase static shift registers, one communicating in parallel with all the bits of the odd words, the other with all the bits of the even words. Each shift register -C-0983. with performs well up to a clock frequency of 1 NlHz. A multiplexer interleaves the odd-even data stream at the one I/O pin, resulting in a maximum data rate of at least 2 Rlb/s. An off-chip four-into-one multiplexer ultimately converts the 64-bit sequence from four parallel chips into the 256-word block transferred at four times the frequency. an addressed block represented by 64 memory transistors on each chip is erased by the application of a 1 ms 30-V pulse. The second step utilizes the information previously placed in the shift registers to inhibit the threshold voltagr change in predetermined locations of the addressed block, when a 1-ms, 30-V write pulse is applied.Testing has indicated that retention of information is orders of magnitude of years, when a specific chip is in a nonaddressed condition at 25OC; Figure 2. When a worst-case stuck-in-one address situation exists, retention is in excess of one year; Figure 3.While for present purposes, the chip is mounted in a 40-lead ceramic dual in-line paekage; the number of functi...

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