No abstract

h OVER THE PAST few years, the 22-nanometer (nm) design has become prevalent in digital circuits to increase the circuit density while the frequency of radio-frequency (RF) circuit has roared up to 60 GHz, or even higher, to satisfy the increasing demand of mobile multimedia communication. Consequently, the complexities of post-layout level verification during parasitic extraction, transient and RF periodic-steady-state (PSS) simulations have increased significantly. The development of parallel algorithms tackles this issue by inventing new approaches towards parallel circuit simulation in electronic design automation (EDA).Recently, multicore CPUs and many-core GPUs have become widely adopted with largely reduced cost. Because of the increasing popularity of parallel hardware platforms, revolutionary development from sequential algorithms to their parallel counterparts is taking place in the software development community, including EDA.However, circuit simulation algorithms for designs at the extreme scale beyond 22 nm and 60 GHz are difficult for parallelization. Because of the nature of circuits, the circuit simulation algorithms usually deal with sparse matrices, as most components are sparsely interconnected with a few others components [1], [2]. Unlike dense algebra operations, algorithms for sparse data structure show irregular data dependence patterns [1]. At the same time, parasitics and EM coupling can result in strong correlation and hence also strong data dependency. As a result, the algorithms for circuit simulation cannot be effectively parallelized by simply unfolding ''for'' loops into parallel code.Most EDA algorithms, especially circuit simulation algorithms, are relevant to graph algorithm or linear algebra [3]. To efficiently parallelize these algorithms on multicore CPUs and many-core GPUs, a few recent innovations of parallelization have been proposed [4]-[7] by reformulating the original irregular or coupled data into structured data with eliminated dependency. For example, board-block-diagonal (BBD) matrix formulation is deployed for the sparse MNA matrix with inverseinductance [4]; fast-multiple-method (FMM) formulation is deployed for capacitance extraction in the presence of stochastic variations [5]; simplified Editors' notes:The authors present a methodology geared towards EDA applications such as parasitic extraction, transient circuit simulation, and RF steady-state simulations.

No abstract

No abstract

No abstract