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This paper describes the generation of the test view of the multiplier-accumulator which is based on a modified Booth algorithm. It will be shown that an algorithm can be found that generates very quickly the test patterns as a function of the parameters of the module. The fault model used is an extension of the traditional stuck-at model towards switch level faults occuring in pass transistor logic. In order to achieve full testability, only slight modifications on the hardware of the multiplier-accumulator were necessary. It was even possible to generate a set of test patterns which is independent of the size of the multiplieraccumulator.

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