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With growing complexity of System on Chip architectures and difficul time to market requirements, early design planning is very important. Design planning for physical design involves the deriving of information, useful to physical implementation of the chip, from the early design information available. Clock tree design and synthesis being a vital part of the design cycle, requires immense planning and experimentation. This paper proposes a way by which key clock tree information can be derived from as early as the register transfer level description of the design. The proposed methodology aids in analysing the clock tree structurally for being friendly to clock tree synthesis. It also enables the prototyping of the clock tree synthesis to understand the overhead it adds to the design. This information can be used to apply corrective feedback to the clock architecture and the physical implementation flo . The various aspects of the clock tree the flo generates along with their utility are presented in the paper with some testcase data. 10th Int'l Symposium on Quality Electronic Design

Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This paper proposes a technique for clock gate optimization to aid clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The method involves employing the "kmeans clustering algorithm" to geographically partition the design's registers. This enables better clock tree quality entitlement during clock tree synthesis in terms of clock tree area, power and better local skew distribution. The paper highlights the utility of this technique by showcasing the clock tree synthesis quality of results improvement on a complex design.