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Abstract-Modern superscalar processors implement register renaming by using either RAM or CAM tables. The design of these structures should address their access time and misprediction recovery penalty. While direct-mapped RAMs provide faster access times, CAMs are more appropriate to avoid recovery penalties. Although they are more complex and slower, CAMs usually match the processor cycle in current designs. However, they do not scale with the number of physical registers and the pipeline width.In this paper we present a new hybrid RAM-CAM register renaming scheme, which combines the best of both approaches. In a steady state, a RAM provides the current mappings quickly; on mispeculation, a low-complexity CAM enables immediate recovery and further register renaming. Compared to an ideal CAM in a 4-way state-of-the-art superscalar microprocessor, and for almost the same performance (1% slowdown) and area (95% of the ideal CAM size), the proposed scheme consumes about 90% less dynamic energy. I. INTRODUCTIONHigh performance microprocessors implement out-oforder and speculative execution to increase performance. In this context, many mechanisms have been devised aimed at enhancing the amount of instructions executing concurrently. These microarchitectural mechanisms require register renaming techniques in order to overcome write after read (WaR) and write after write (WaW) data hazards.Register renaming techniques distinguish two kinds of registers: logical and physical registers. Logical or architected registers refer to those used by the compiler, while physical registers are those actually implemented in the machine. Typically, the number of physical registers is quite larger than the number of logical registers. When an instruction that produces a result is decoded, the renaming logic allocates a free physical register. Then, the destination logical register is said to be mapped to that physical register. After that, subsequent data dependent instructions rename their source logical registers to access this physical register. In addition, to deal with program execution correctness, the register renaming circuitry must also recover the register mapping table on mispeculation and release the physical registers allocated to mispeculated instructions. To this end, some microprocessors perform checkpoints of the renaming

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