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Background: Complete Ternary Adder is the prime building block for Ternary Carry Save Adder (TCSA) and acts as a critical deciding factor to optimize the overall speed-power performance for many complex ternary computing like ternary multiplication. Objective: This work targets to propose a new idea for high-speed complete Ternary Adder design with reduced Power-Delay-Product (PDP) using PTL (Pass Transistor Logic) based novel 3:1 Ternary Multiplexer (T-MUX) for efficient ternary computing. Materials: No external materials have been used for the present work. Methods: In the proposed approach a novel 3:1 T-MUX with conventional E-MOS (Enhancement-type Metal Oxide Semiconductor) transistor is designed first. Novel Select Unit (SU) and Control Unit (CU) are the prime building blocks for the proposed T-MUX circuit and are also disclosed. The 3:1 T-MUX is exploited next to achieve the proposed high-speed, low-PDP Ternary Half and Full Adder operation. The complete adder circuit is designed and optimized based on BSIM4 device parameters using 32nm standard CMOS technology with 1.0V supply rail at 27°C temperature. Trit values “0”, “1” and “2” are represented with 0V, 0.5V and 1.0V respectively. Extensive T-Spice simulation with all possible test patterns using PWL (Piece Wise Linear) input source validates the proposed circuit. The evaluated speed-power result of the proposed TFA is then compared with the most recent competitive study to benchmark. Experimental Results: The proposed complete TFA offers 68.9% and 82.5% reduction in propagation delay along with 27.7% and 31.6% Power-Delay-Product (PDP) reduction compared to the most recent competitive complete TFA Design-1 and Design-2 respectively. Discussion: As per study the proposed idea can be a good choice to produce fast ternary addition along with reduced Power-Delay-Product (PDP). Conclusion: The proposed complete TFA can be utilized effectively as Ternary Carry Save Adder (TCSA) for fast, low-PDP ternary multiplication as well as for other computation intensive applications.

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Present study explores novel self-pipelining strategy that can enhance speed-power efficiency as well as reliability of binary multiplier as compared to state-of-art register and wave-pipelining. Proper synchronization with clever clocking between subsequent Self-pipelining stages has been applied to achieve proposed self-pipelined multiplier. Each self-pipelining stage consists of self-latching leaf cells and are designed, optimized and evaluated on TSMC 0.18µm CMOS technology with 1.8V supply rail and at 25°C temperature. The T-Spice transient response and simulated results for the designed circuits are presented. The proposed idea has been applied to design 4-b×4-b self-pipelined Wallace-tree multiplier. The multiplier is validated for all possible test patterns and the transient response is included. The circuit performance in terms of propagation delay, average-power and Power-Delay-Product (PDP) is recorded. Next, the decomposition logic has been applied to design some higher order multiplier (i.e., 8-bit×8-bit and 16-bit×16-bit) based on proposed strategy using 4-bit×4-bit self-pipelined multiplier. The designed multiplier also has been validated through extensive T-Spice simulation for all required test pattern using W-Edit and the evaluated performance is presented. All the designs, optimizations and evaluations are performed based on BISM3 device parameter on TSMC 0.18µm CMOS technology with 1.8V supply rail at 25°C temperature using S-Edit of Tanner EDA. The reliability has been investigated with respect to proposed 4-b×4-b multiplier in the temperature range -40°C to 100°C for maximum PDP variation. A benchmarking analysis in terms of speed-power performance with recent competitive design reveals superiority of proposed idea.

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