This paper encompasses the implementation of a novel approach to an 8-bit digital multiplier based on Ancient Indian mathematical algorithm (also known as the Vedic sutra) and its comparison with 2 other conventional multipliers. Since multiplication has become a fundamental function in applications such as Fourier transform, Arithmetic Logic Unit (ALU) architecture and in various sequential clocked circuits, an efficient multiplication technique is a major concern for computer architects. The three multipliers were programmed in Verilog, simulated on Xilinx 14.5 ISE and implemented on 2 FPGA devices, Spartan 3E and Spartan 6. A comparison based on empirical values of delays of each multiplier throws a light on their potential in making the digital circuits substantially efficient.