For efficient digital FIR filter applications, the Multiplication and Accumulation (MAC) unit is implemented by using various methods. In a digital filter, the MAC unit is one of the main units for performing multiplications and additions. This paper presents an efficient filter design for digital signal processing (DSP) applications with the reduction of carry propagation. In general, the performance of transpose filter mainly depends on the design of MAC unit. The design of a traditional filter consists of a large number of logical elements and has a high computational delay due to the conventional MAC unit. To design an efficient MAC unit, a serial adder is employed by using 2:1 multiplexer and a shifter block. The proposed work is implemented by using Xilinx ISE synthesis tool.

Software Defined Radio (SDR) is a new technology used to implement different wireless communication standard for mobile communication. The Intermediate Frequency (IF) block is the most demanding block in software defined radio. The most important task in intermediate processing block is digital filtering which is carried out by Finite Impulse Response (FIR) filter. One of the major techniques for the calculation of inner product is Distributed Arithmetic (DA) based FIR filter which uses Look Up Table (LUT) to eliminate the need of multiplier. The efficiency of the DA filter is affected with the increasing number of address line and also due to its serial operation. To overcome this problem parallel and pipeline based DA filter using Offset Binary Coding (OBC) for Two Bit At A Time (2-BAAT) is proposed. Our proposed method achieves less area, low power consumption and nominal delay for SDR application.

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