Reconfigurable processor architectures can dynamically switch their instruction set and instruction format at run time. They offer a new flexibility for adapting to changing applications' requirements in order to optimize performance and enable resource-awareness. While programmability is a key issue of such architectures, today's software toolchains are limited to static ISA architectures and must be extended to support reconfigurable processors that can expose different ISAs at run time. In this paper, we address this shortcoming by presenting a novel retargetable software toolchain that is suitable for mixed-ISA application development as well as design space exploration (DSE). Therefore, we developed a novel mixed-ISA, compiler-and simulator-centric, behavioral architecture description language (ADL). The ADL provides the necessary flexibility to describe multiple ISAs for the software framework. The individual framework tools -the compiler, binary utilities, and instruction set simulator (ISS) -are generated from an ADL description. To realize the complex compiler inside the framework, we extended the LLVM compiler infrastructure by a mixed-ISA retargetable code generator (compiler back-end). To illustrate the flexibility of the ADL-based software toolchain, we performed a first DSE for application characterization of a variety of multi-domain applications. To show the feasible performance/resource benefits through dynamic reconfiguration, we further developed a mixed-ISA application that can dynamically change its instruction format at run time.

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The mapping process of high performance embedded applications to today's reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware - introduced by software parallelism of multiple cores and the flexibility of reconfigurable architectures - to the end user. The Architecture oriented paraLlelization for high performance embedded Multi-core systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab- and architecture-description-language-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction. This holistic solution of the tool chain allows the complexity of both the application and the architecture to be hidden, which leads to a better acceptance, reduced development costs, and shorter time-to-market

Reconfigurable tile-based architectures can dynamically interconnect several tiles in order to establish processor instances with varying resource, performance, and energy characteristics at run time. These flexible processor instances offer a new degree of freedom for adapting to changing applications' requirements while optimizing resource and energy consumption. Our solution for dynamic interconnection of tiles requires a flexible Run-Time Scalable Issue-Width (RSIW) Instruction Set Architecture (ISA) that changes dependent on the configuration. In order to enable high-level programmability of our architecture in C/C++ a novel compiler back-end is needed. In this paper we address this necessity by presenting a novel LLVM compiler back-end targeting the reconfigurable RSIW ISA and supporting mixed-ISA software development. RSIW is comparable to clustered-VLIW ISAs since it expresses parallel operations within the ISA and explicitly uses clustered register files. Therefore, we extended our architecture description language based RISC LLVM back-end by representations of parallel operations as well as compilation passes for clustering and scheduling of parallel operations as well as mixed-ISA code generation. Based on the novel back-end we compare the performance characteristics of several applications compiled for and simulated on different configurations. Additionally, we demonstrate resource-aware reconfiguration by a mixed-ISA application scenario.

The sustained advance in technology will enable integrating hundreds of processing cores on a single die in near future. However, it already can be foreseen that the management of the resources of such large systems will not scale in the same way as the hardware using todays entirely software based and centralized management approaches. The invasive paradigm addresses this problem and proposes concepts to enable resource awareness and scalability -especially focusing the resource management perspective -in future multicore systems. These concepts are based on distributed and software-hardware partitioned resource management strategies. High level management decision that are made by software thereby trigger lower level management strategies that are autonomously carried out in hardware. Sufficiently accurate modeling of the overall invasive system is required to study and optimize such a decentralized, software-hardware partitioned control loop where decisions significantly depend on runtime dynamic effects. Software based simulation cannot deliver the required speed or accuracy making FPGA based prototyping of invasive systems necessary. This paper describes our prototyping concepts and discusses possible implementation alternatives for invasive multicore architectures.