Multiplication is a crucial function and plays a vital role for practically any DSP system. Several DSP algorithms require different types of multiplications, specifically modified booth multiplication algorithm. In this paper, a simple approach is proposed for generating last partial product row for reducing extra sign (negative bit) bit to achieve more regular structure. As compared to the conventional multipliers these proposed modified Booth's multipliers can achieve improved reduction in area 5.9%, power 3.2%, and delay 0.5% for 8 x 8 multipliers. We can also observe that achievable improvement for 16 x 16 multiplier in area, power, delay are 4.0%, 2.3%, 0.3% respectively. These multipliers are implemented using verilog HDL and synthesized by using synopsis design compiler with an Artisan TSMC 90nm Technology
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