Cryptography is commonly employed in data security, but one of the main disadvantages of the scheme would be that it attracts attention to just the perpetrator, which results throughout the exposure of the data. In order to solve these issues, digital image steganography is among the several techniques used to provide protection during data transmission. Capacity embedding and distortion are indeed the two key factors that play a key role when hiding a message in image. Therefore, this paper explores strategies consisting of two steps leading to the creation of that very stable framework with a large embedding ability. The first step determines an arbitrary image by morphing through hybrid discrete wavelet transform (HDWT) in order to produce a cover image that relies on the characteristics of both the chosen image. That second step integrates a text message of adequate duration using the transfer learning based ResNet50 architecture, integrating multi-keys and compound operators into the algorithm to provide robust protection. Simulation results shows that the proposed method resulted in superior PSNR and SSIM performance as compared to state of art approaches.Finally, the robustness and imperceptibility of the proposed method is improved, which reduced the attacks on the system.

SRAM is a key component in many VLSI circuits for efficient storage data. Various researches have been performed on implementation of SRAM using Conventional CMOS, FinFET and GNRFET technologies. But, these methodologies generating the more number of faults with high power and delay consumption, tosolve this problem proposed10T SRAM cell is implemented with the CNTFET respectively. Present research involving CNTFET SRAM deals with leakage analysis and dealt with the dual hilarity characteristics. Fault introduction and analysis of faults were limited with CMOS SRAM. The detection algorithms and circuits possess limitations in terms of detecting the current at nanoscales and restricted with CMOS SRAM. These limitations made us to pursue the research in these areas to bring novel ideas. The performance metrics evaluated and experimental analysis is made and it helps us to choose between various SRAMS. The simulation results shows that the proposed 10T SRAM consumes less delay and power compared to the 7T SRAM cell.