Malicious applications target Multi-Processors System-on-Chip (MPSoCs) to capture sensitive information or disrupt normal operation; therefore, security is now a design requirement for MPSoC design. Network-on-Chip (NoC) is a key communication structure to aid in the overall MPSoC protection. Firewall-based NoC protection allows data exchange monitoring and controlling according to the MPSoC security policy. Secure NoCs enable to detect and prevent a broad range of software-based attacks. However, complex security policies may turn firewalls costly. This paper proposes a protection technique based on the NoC routing algorithm. By manipulating the routing of packets, security zones can be built. Our routing algorithm prioritizes communication among paths deemed secure while guaranteeing deadlock freedom. We evaluate the scalability of the proposed technique using synthetic and real application scenarios, as well as the security of the proposed technique

This paper presents a complexity analysis of 3D High Efficiency Video Coding (3D-HEVC) depth maps intra prediction. The 3D-HEVC inserts new coding tools in depth maps intra prediction such as Depth Intra Skip (DIS), Depth Modeling Modes (DMMs) and Segment-wise DC (SDC). Therefore, it is important to understand the complexity of each module to allow the design of new complexity reduction techniques to encode the depth maps. This paper aims to guide other works to the most time-consuming tools that could be simplified to achieve a realtime design according to the encoding context.

Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are currently exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infecting IP-blocks connected to a Network-on-Chip (NoC) and opening doors to perform Timing Side Channel Attacks (TSCA). By monitoring the NoC traffic, an attacker is able to infer the sensitive information, such as secret keys. Previous works have shown that NoC routing can be used to avoid attacks. In this paper we propose GRaNoC, a NoC architecture able to monitor and evaluate the risk of the communication paths inside the NoC. Sensitive traffic is exchanged to minimal low-risk paths defined at runtime. We propose five types of dead-lock free risk-aware routing algorithm and evaluate the security, performance and cost under several synthetic and SPLASH-2 benchmarks. We show that our architecture is able to guarantee secure paths during runtime while adding only low cost and performance penalties to the MPSoC

Following the current trend in the semiconductor industry (MPSoC) and the massive advances presented by all things interconnected (Internet of Things), a massive quantity of private and metadata is being transferred through insecure channels. In the industry, almost no attention is given to the amount of data that can be collected from different individuals, just by getting access to their house appliances. With that in mind, this paper proposes a non-intrusive and reconfigurable access control architecture for Networks-on-Chip (NoCs). This architecture comprises firewalls, which are capable of filtering both incoming and outgoing network traffic by analyzing packet information and verifying a traffic initiator's access permission, providing a secure environment that is capable of protecting the user data. The firewalls have approximately 12% of the router area. When the number of routers increases, the firewall area overhead grows slightly, up to only 16% in NoCs with 64 routers.

Parallel applications are essential for efficiently using the computational power of a Multiprocessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale effortlessly with the number of cores because of synchronization operations that take away valuable computational time and restrict the parallelization gains. Moreover, synchronization is also a bottleneck due to sequential access to shared memory. We address this issue and introduce "Subutai", a hardware/software (HW/SW) architecture designed to distribute essential synchronization mechanisms over the Network-on-Chip (NoC). It includes Network Interfaces (NIs), drivers and a custom library of a NoC-based MP-SoC architecture that speeds up the essential synchronization primitives of any legacy parallel application. Besides, we provide a fast simulation tool for parallel applications and a HW architecture of the NI. Experimental results with PARSEC benchmark show an average application speedup of 2.05 compared to the same architecture running legacy SW solutions for 36% overhead of HW architecture.