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SUMMARYThis paper is adopting a new approach to investigate the capabilities of pathological mirror elements in the ideal representation of active building-blocks and shows that the voltage mirror (VM) and current mirror (CM) are the basic pathological elements. The descriptions for the floating mirror elements in the nodal admittance matrix (NAM), using infinity-variables, are derived. The descriptions for nullator and norator using infinity-variables in the NAM are shown to represent special cases from the derived descriptions of the floating VM and the CM, respectively. Hence, new representations for the nullator and norator in terms of the floating VM and CM, respectively, are obtained. A systematic procedure for the derivation of pathological configurations to ideally represent various analog signal-processing properties featured by active building-blocks is presented. This systematic approach became plausible by virtue of the versatility offered by the NAM descriptions of floating mirror elements. Novel pathological configurations ideally describing most popular signal-processing properties that involve differential or multiple single-ended signals; like conversion between differential and single-ended voltages, differential voltage conveying, current differencing, differential current conveying, and inverting current replication; are derived systematically using this procedure. The resulting pathological configurations are shown to be constructed mainly using mirror elements and hence the capabilities of the mirrors as basic pathological elements are further demonstrated. Pathological representations for some active building-blocks, using the derived pathological sections, are presented as application examples.

SUMMARYIn this paper, CCII-based gyrators are synthesized, modeled, and analyzed using the generalized symbolic framework for linear active circuits. The systematic synthesis method using admittance matrix expansion, included in the framework, is applied to generate optimized nullor-mirror descriptions for the gyrator. The resulting CCII-based circuit representations for the gyrators, obtained from mapping nullor-mirror pairs in the ideal realizations with equivalent second-generation current conveyors (CCIIs), can be classified into two topologies according to the type of the CCII terminals handling the gyrator input and output signals. In topology I, the gyrator input and output terminals are CCIIs Y -Z -terminals, whereas in topology II, the gyrator input and output terminals are CCIIs X -terminals. The parasitic components within the synthesized circuits, associated with the actual CCIIs, are modeled and included in their expanded admittance matrices. Exact non-ideal analysis for two circuits belonging to the two topologies, involving the reduction of their expanded admittance matrices to port admittance matrices, is then carried out to investigate the practical functional performance for these circuits at their ports. The non-ideal performance analysis based on the CCII actual parasitic elements indicates that, from a practical perspective, the CCII-based gyrator circuits belonging to topology I are more efficient and suitable for the gyrator applications than those belonging to topology II in terms of bandwidth and operation at high frequencies. SPICE simulations are included to demonstrate the analytical results for the comparison between the practical performances of the two circuit topologies.

SUMMARYThis paper is adopting a new approach in the systematic synthesis of CCII-based floating simulators. The synthesis procedure is based on the generalized systematic synthesis framework for active circuits using admittance matrix expansion. The resulting derived floating simulators include circuits that have been reported earlier in the literature in addition to novel floating simulators using various types of CCII. The synthesized floating simulators can be used to realize floating coils, FDNRs, and resistance and capacitance multipliers; according to the types of passive elements employed in the design. The potentials and drawbacks of every one of the synthesized circuits vary according to the design tradeoffs including complexity, number of active devices, number and values of grounded and floating passive elements, matching requirements, and tunability. SPICE simulations are presented to verify the performance of the new circuits obtained by systematic synthesis and hence demonstrate the potentials of the generalized synthesis framework in producing novel circuits with high performance.