No abstract

Three-dimensional (3-D) stacking of integrated circuits (ICs) using through-silicon-vias (TSVs) is a promising integration platform for next-generation ICs. Since TSVs are not fully accessible prior to bonding, it is difficult to test the combinational logic between scan flip-flops and TSVs at a prebond stage. In order to increase testability, it has been advocated that wrapper cells (WC) be added at both ends of a TSV. However, a drawback of WC is that they incur area overhead and lead to higher latency and performance degradation on functional paths. Prior work proposed the reuse of scan cells to achieve high testability, thereby reducing the number of WC that need to be inserted; however, practical timing considerations were overlooked and the number of inserted WC was still high. We show that the general problem of minimizing the WC is equivalent to the graph-theoretic minimum clique-partitioning problem, and is therefore NP-hard. We adopt efficient heuristic methods to solve the problem and describe a timing-guided and layoutaware solution. We evaluate the heuristic methods using an exact solution technique based on integer linear programming. We also present design-for-test optimization technique to leverage the reuse-based method during post-bond testing. Results are presented for 3-D-stack implementations of the ITC'99 and the OpenCore benchmark circuits. Index Terms-Automatic test pattern generation (ATPG), design-for-test (Df T), three-dimensional (3-D)-stacked integrated circuit (IC), through-silicon-via (TSV).

No abstract

No abstract

Modern high-performance designs require accurate on-chip timing uncertainty measurements for post-silicon validation of high speed interfaces and clock distribution networks. On-chip timing measurements capabilities must keep up with growing design complexity and process variations to meet competitive product time-to-market. However, enhancing silicon debug capabilities cannot simply be met by proliferating on-chip structures, since the overhead would be prohibitively expensive to deploy. We propose moving on-chip debug and validation structures onto a separate die which would be stacked onto the product die using three-dimensional integration (3D-IC). This paper focuses on achieving observability at clock sinks which are critical for understanding on-chip timing uncertainty. We present a circuit implementation and design flow which realizes high volume on-chip timing measurements for a 2D product die.