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Technology scaling in deep-submicron devices has increased the susceptibility of integrated circuits to radiation. Single event effect (SEE) is one of the major radiation influences that can provoke transient errors in the circuit. SEE can occur even in the clock distribution networks. During the strike of an ionizing particle, charge may be collected on the output node of the clock buffer provoking a clock glitch, clock jitter and skew. As consequence, it is possible to notice errors in circuit functional behavior. This paper investigates the soft-error probability due to SET in clock tree networks proposing a methodology to any ASIC layout circuit. This methodology allows finding 4.6% of registers with high susceptibility in a SRAM arbiter circuit.

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