Abstract. An ESOA of LDMOS device is very critical for power device performance. Kirk effect is the one of the major problem which leads to poor ESOA performance. The cause of the problem mainly due to the high beta value of parasitic NPN transistor in the p-body. In this study, we proposed a new 3D high side SideIsolated N-Channel LDMOS which we have obtained not only benchmark Ron and breakdown performance, but also better ESOA without Kirk effect. We have compared the analysis of Kirk effect between the new device and the conventional N-LDMOS structure with LATID technique for the formation of the p-body of both device structures.

In this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve better ESOA performance while maintaining a benchmark specific on-resistance with breakdown voltage over 120 Volts. The key feature of this novel device is linear p-top rings which are located in the n-drift region. Optimization of p-top mask design and n-drift region concentration is performed in order to achieve the lowest on-resistance possible with the desired breakdown voltage.

In VDMOS device the anti-JFET concentration has important role for determining the breakdown voltage and on-resistance of the device. Because higher N-drift doping concentration can provide the very best on-resistance of the device but also decrease breakdown voltage. It also has a proportional relationship with threshold voltage degradation. In this paper, we report the anti-JFET implantation energy influence effect electric potential distribution, the highest impact ionization shifted from the silicon surface to deeper. It will have less hot carrier impact, and we have found higher breakdown voltage. The anti-JEFT implantation is critical for on-resistance off-state breakdown voltage optimization, However the high field and high impact ionization near the gate region will cause severe hot carrier Injection problem. The general expectation of high voltage VDMOS transistor is to have higher breakdown voltage, less degradation due to hot carrier injection and better on-resistance.

In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat degradation at low gate voltage (VGS) and high drain voltage (VDS) is investigated. Hot Electrons, generated by impact ionization during stress, are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel. Increase of the drain-source current is induced by the negative fixed oxide charges. The physical model of the degradation has been proven combining experimental data and TCAD simulations.