Abstract-With the increasing number of voltage conversions that have to be efficiently implemented in a mobile device, the PCB space occupied by switched-mode DC-DC converters with external passive components will become unacceptably high. Therefore, a clear need exists for small-form-factor high-efficiency DC-DC converters having the necessary passive components integrated within one package. This will enable the integration of a DC-DC converter with the load and consequently the system integration of power management. This paper describes the measurement results of an integrated inductive down converter, where the active electronics (power stage and driver circuitry) has been implemented in 0.18-μ μ μ μm CMOS technology and the passive components (output LC filter and decoupling capacitor) have been implemented in a stateof-the-art proprietary passive-integration process technology using high-density trench-MOS capacitors (80 nF/mm 2 ) and an 8-μ μ μ μm thick copper top metallization layer. The active die of the converter has been flip-chipped on top of the passive die to reduce parasitic component values. This yields a System-in-Package (SiP) that achieves a step-down DC-DC conversion without any external components. Due to the limited inductance achievable with the used planar air coil in the acceptable area, the switching frequency of the DC-DC converter has been increased. At the same time, Zero-Voltage-Switching (ZVS) measures have been implemented to reduce the switching losses at this increased frequency. A maximum efficiency of 65% at 80 MHz has been achieved for an input voltage of 1.8 V, an output voltage of 1.1 V and an output current of 100 mA. After explaining the motivation behind integrated power management and the choice for an integrated inductive converter, this paper describes the main design aspects of the realized integrated inductive DC-DC down converter. Next, it presents some details of the used passive-integration process, the design of the passive die including the LC filter and the construction of the SiP. Finally, the measurement results of the converter are discussed and conclusions are drawn.

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-This paper describes the design and measurement results of a supply modulator for a PA for GSM, EDGE and UMTS application. The modulator combines a high-bandwidth class-AB linear regulator with an efficient DC/DC converter in a master-slave configuration. The DC/DC converter is currentmode controlled and has been designed to operate at switching frequencies between 1MHz and 25MHz. A damped dualinductor LCR filter has been inserted in the output branch of the DC/DC converter for ripple suppression. The chip has been fabricated in a 0.25µm CMOS process with an additional gate oxide for 6V transistors and has an active area of 1.5mm 2 . It achieves a bandwidth of 50MHz (for UMTS) with a peak output power of 3.2W (for GSM) and output rms ripple of less than 4mV.

Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication Citation for published version (APA):Bergveld, H. J., Nowak, K., Karadi, R., Iochem, S., Ferreira, J., Ledain, S., ... Pommier, M. (2009). A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration. In Proc. IEEE Energy Conversion Congress and Exposition (ECCE'09), San Jose, USA, 20-24 Sept. 2009 (pp. 3698-3705 General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract --The increasing number of efficient voltage conversions realized in small volumes in many applications has introduced a trend towards small-form-factor DC-DC converters with integrated passives. Preferably, the DC-DC converter is integrated with the load, often in nm-CMOS, allowing for local supply optimization yielding increased power efficiency. However, energy-storage densities in nm-CMOS are low and silicon area is expensive. Therefore, to limit cost of monolithically integrated systems, passive components have low values, leading to very high switching frequencies, which compromises efficiency. This paper follows an alternative approach, where the active converter part is realized in 65-nm CMOS and the passive part in a low-cost high-density passiveintegration process. With the active die flip-chipped on the passive die a small System-in-Package (SiP) is obtained with a peak efficiency of 87.5% at 100 MHz switching frequency and 85 mW output power. This performance is mainly caused by the high quality of the integrated passives.