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Analog integrated circuit design is widely considered a time-consuming task due to the acute dependence of analog performance on the transistors’ and passives’ dimensions. An important research effort has been conducted in the past decade to reduce the front-end design cycles of analog circuits by means of various automation approaches. On the other hand, the significant progress in high-performance computing hardware has made machine learning an attractive and accessible solution for everyone. The objectives of this paper were: (1) to provide a comprehensive overview of the existing state-of-the-art machine learning techniques used in analog circuit sizing and analyze their effectiveness in achieving the desired goals; (2) to point out the remaining open challenges, as well as the most relevant research directions to be explored. Finally, the different analog circuits on which machine learning techniques were applied are also presented and their results discussed from a circuit designer perspective.

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this paper describes a Design Of Experiments (DOE) based method used in computer-aided design to simulate the impact of process variations on circuit performances. The method is based on a DOE approach using simple first and second order polynomial models with multiple experiment maps. It is a technology & circuit-independent method which allows circuit designers to perform statistical analysis with a dramatically reduced number of simulations compared to traditional methods, and hence to estimate more realistic worst cases, resulting in a reduced design cycle time. Moreover, the simple polynomial models enable direct linking of performance sensitivity to process parameters. The method is demonstrated on a set of circuits. It showed very accurate results in linking linearity, gain and noise performances to process parameters, for both RF and analog circuit.