This paper introduces an extension of Timed Petri Nets for the modeling of synchronous electronic circuits, addressing pipeline design problems. Petri Nets have been widely used for the modeling of electronic circuits. In particular, Timed Petri Nets which capture timing properties are perfectly suited for scheduling problems. Our extension, through reset that model the pipeline stages, and through delayable transitions that relax timing constraints, allows to widen the conception space of pipelined systems. After discussing maximal-step firing rule and the semantics of Timed Petri Nets "à la Ramchandani", we define our Timed Petri Nets with reset and delayable (non-asap) transitions. We then study the decidability and the complexity of the main problems of interest. We propose an abstraction of the state space. We then establish a translation of this model into a single-clock timed automata, which preserves the language. This translation settles the decidability on language inclusion and universality problems. Finally, an algorithm for the exploration of the state space is provided, and can be driven by the optimisation of various properties of the pipeline.

A major step in arithmetic operators design is the placement of pipeline stages, with the goal of drastically increase the data throughput.Approaches, such as the as-soon-as-possible greedy algorithm, allow pipelining with a frequency target. They can possibly be combined with a retiming operation to reduce the number of pipeline registers. This retiming step is based on a weighted directed graph model, from which the pipeline placement is reduced to an optimisation problem (for example ILP). However, this approach produces only a unique solution, and makes it difficult to add additional constraints on the resulting pipeline.We propose to use a Timed Petri Net extension with cost, where time captures the propagation delay and cost measures the size of pipeline registers. The state space of the model captures exactly the circuit states and the branching points, so its exploration can be guided by comparing the circuit states regarding any feature (number and size of registers, critical path, throughput, etc). The pipeline exploration can be reduced to a weighted branching-time logic model-checking problem, that we prove to be PSPACEcomplete on this model.We have implemented this exploration algorithm in a prototype tool. We apply it on some arithmetic operators provided by FloPoCo showing improvements up to 35% compared to the current implementation.

A fundamental step in circuit design is the placement of pipeline stages, which can drastically increase the data throughput. The retiming allows optimizing the pipeline with regard to a criterion, for example the required number of registers. This article presents an extension of Timed Petri Net to model synchronous electronic circuits, in order to explore the design space of pipelines.The Timed Petri Nets à la Ramchandani with a maximal step ring rule, have been notably used for the modeling of electronic circuits.The RTPN extension, through the reset which model the pipeline stages, and through the delayable transitions which relax some temporal constraints, makes possible to widen the design space of pipelined systems, and thus to deal with both the retiming and the verication.After a formal denition of this model, we present a method to explore pipelines verifying temporal properties. We apply our approach to a time-multiplexing property allowing the mutualization of operators while minimizing the number of registers.

We address the problem of computing the infimum accumulated weight for the reachability of some goal location in weighted timed automata. While there already exist efficient techniques to solve this problem, we propose here a backwards symbolic algorithm computing the accumulated weight to the goal, instead of the accumulated weight from the initial state. Going backwards has in itself a few advantages: most notably it does not require any extrapolation operation to ensure termination. Also it may be more efficient than going forward if the set of co-reachable states is smaller than the set of reachable states. Backwards algorithms are also instrumental in several problems beyond reachability, like control problems for instance. We obtain our backward algorithm by proposing extensions of the classical action and time predecessor operations on zones to account for weights. We have implemented the approach and report on its performance.