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Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface design has been a time-consuming process. This paper proposes a novel and efficient approach to designating pinout for flip-chip BGA package when designing chipsets. The proposed approach can not only automate the assignment of more than 200 I/O pins on package, but also precisely evaluate package size which accommodates all pins with almost no void pin positions, as good as the one from manual design. Furthermore, the practical experience and techniques in designing such interface has been accounted for, including signal integrity, power delivery and routability. This efficient pin-out designation and package size estimation by pin-block design and floorplanning provides much faster turn around time, thus enormous improvement in meeting design schedule. The results on two real cases show that our methodology is effective in achieving almost the same dimensions in package size, compared with manual design in weeks, while simultaneously considering critical issues in package-board codesign. To the best of our knowledge, this is the first attempt in solving flip-chip pin-out placement problem in package-board codesign.

Fig. 1. The placement of pin-blocks and IPs. (a) shows the worse pin-out assignment where the pin-block located around the package comer can not meet the objectives of shorter path length and equi-Iength on package routing. (b) shows our novel planning algorithms can overcome the drawbacks in (a).In this paper, we develop an improved pin-block planner to overcome the drawbacks mentioned above. Our methodology applies simulated annealing based heuristic by using a representation suitable for pin-block placement, and defining range constraints to optimize the location of pin-blocks and to minimize the wirelength. Our ideas also work for any kind of pin-block or pin-group configurations. The rest of this paper is organized as follows. We first define the constraints of pin-block planning in Section II. Section III describes the improved pin-block planner with Cyclic Number Set (eNS) representation, and formulates the cost function with placement deviation. Section IV shows the experimental results followed by conclusions in Section V. II. PIN-OUT PLANNING FOR OPTIMIZING PACKAGE PERFORMANCE AND BOARD WIRE-PLANNINGIn the usual design flow, the designers determine the pin configuration chart based on experience about the location of component on PCB and the characteristics of each signal group. The pin configuration chart defines all critical parameters including the distribution region (side), placement sequence (order), selected signal-pin pattern and the number of power pins. According the definition of this chart, the designers finish the pin groups (or blocks) construction for all signal groups. Next, all pin-blocks will be placed along the defined side and order in which the first placed pin-block is located at the fixed location. Finally, after obtaining a rough pin-out designation and estimating the minimum package size, the pin-block floorplanning algorithm bends the pin-blocks allocated in the excess regions and shifts them into the adjacent empty regions. Hence, this shifting technique usually produces the bent pin-blocks located in the package comer without considering the package design for high-speed interface IPs such as USB and PCI Express. Moreover, those constraints defined in pin configuration chart will restrict the margin and flexibility for optimizing the final pin-out. Pin-blockAbstract-In this paper, we propose an improved pin-block placer to optimize the objectives of shorter path length and elJ,ui-length on package routing. This placer keeps tile same mmimizedpackage size as the recent work and ensure that signal integrity (81), power delivery integrity (PI) and routability (KA) can still be considered with significant reduction in desi~n cost. It is achieved by relaxing the restriction of pin-block Side and order on the package, usually specified by package designers. The experimental results on industrial chipset design cases show that the average improvement of our pin-block planner is over 40% when comparing the design cost with the previous work, among which we have one case over a thousa...

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