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A new method for the synthesis of active RC circuits employing multiple output current controlled conveyors (Mo-CCCIIs) is presented here. A new graph is proposed for Mo-CCCII and the application of this graph in active filter design is studied. The obtained active filter uses Mo-CCCIIs as active devices and only capacitors as passive elements without the need of passive resistors. To generalise the proposed method, an algorithm is presented, which converts the loop-cut-set matrices of the passive LC filter prototypes to the proper matrices for Mo-CCCII-based active filters. The new matrices characterise the connections of the equivalent Mo-CCCII-based active filter. The presented algorithm is programmed in MATLAB, so the matrix manipulation is done very quickly. Also, Hspice simulation result of the synthesised active filter is given to confirm the viability of this approach.

High sampling frequency requirement in delta–sigma modulator (DSM) is one of the limiting factors toward its employment in high-frequency application, such as software-defined radio (SDR) transmitters. In this paper, a complexity-reduced parallel time-interleaved DSM is proposed to reduce the clock speed requirement of DSM transmitters. The complexity of the proposed parallel time-interleaved DSM is reduced by input delay blocks and input downsampler blocks in comparison to conventional time-interleaved DSMs. Simulation results show that the clock speed requirement of DSM transmitter is reduced four times by using the proposed four-branch complexity-reduced time-interleaved DSM, while signal quality is maintained.

The polar delta–sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software‐defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitter architecture. This study proposes a low‐complexity time‐interleaved architecture for the polar DSM transmitter baseband part to reduce the clock speed requirement of the polar DSM transmitter using an upsampling technique. Simulations show that using the proposed four‐branch time‐interleaved polar DSM transmitter baseband part, the clock speed requirement of the transmitter is reduced by four times without degrading the signal‐to‐noise‐and‐distortion ratio.