Several next generation integration schemes – e.g. for 3D stacked transistors, backside power distribution, and advanced packaging involve permanent wafer bonding steps and drive to sub-10nm overlay requirements post bonding. Distortion during wafer bonding is a major determinant of best achievable overlay between post to pre bonding lithography layers. Here, we investigate correlations between wafer bonding process and post bonding overlay performance through a combination of experiment and modelling. We use a custom test vehicle to collect wafer distortion data from pre- and post-bond processes, as well as overlay data after the post-bond processing steps (anneal and thin). The results establish direct relationships between incoming wafer distortion, bonder-induced distortion and post-bond lithography overlay to a pre-bond level. We also use the experimental results to validate a wafer bonding simulation model to further physical explanation of process-induced distortion. The experiment results will enable advanced wafer bonding process controls to optimize distortion and scanner overlay to meet technology targets. The results will also help guide hardware design to improve distortion fingerprints to best improve scanner overlay, as well as address the distortion challenges from incoming wafers.

In an earlier publication, we evaluated simulation methods to explore overlay performance implications when a highNumerical Aperture (high-NA) Extreme Ultra Violet (EUV) exposure is mixed and matched with a 0.33NA EUV full field exposure. The present contribution goes beyond the method description and aims to quantify the overlay performance impact in such a mix and match case, giving insight into the influence of different sets of overlay corrections. To this aim, the Mont Carlo engine has been updated to accommodate overlay corrections with up to 57 parameters. Since high-NA EUV is not yet available, typical overlay correction terms from IBM’s 0.33NA EUV tool have been used to approximate a realistic image placement error fingerprint for our simulations. As a result, we demonstrate the benefit of various overlay correction sets, and the detrimental effect when using different masks for top and bottom half fields. Such information can also help to infer design layout placement decisions to avoid hot spot regions.