No abstract

Model based OPC for low k1 lithography has a large impact on mask cost, and hence must be optimized with respect to mask manufacturability and mask cost without sacrificing device performance. Design IP blocks not designed with the lithography process in mind (not "litho friendly") require more complex RET/OPC solutions, which can in turn result in unnecessary increases in the mask cost and turn around time. These blocks are typically replicated many times across a design and can therefore have a compounding effect.Design for manufacturing (DFM) techniques verify and alleviate complex interactions between design and process. DFM can be applied at various stages in your design-to-silicon flow. 1 We will discuss how these DFM methods are applied and implemented at Cypress. We will also show how design rules are defined and present several methods for injecting OPC/RET awareness into the designs prior to mask manufacture.

No abstract

The upcoming 45nm device node is a point at which newer field-based (i.e., dense pixel-based) OPC simulation methods may begin to show advantages over sparse-sampling ("flash") simulation methods. Field-based simulation provides computational efficiencies in applications where a large number of model evaluation locations are needed, and where the simulated layout geometry is complex. Field-based simulation leverages computation in the frequency domain, whereas sparse-sampling methods operate in the space domain. Mathematically, both methods are equivalent but their respective numerical methods give rise to some implementation differences for OPC applications. These differences include different optimization strategies for hierarchical processing, and fine-grained feature symmetry control for critical matched-transistor circuits (such as SRAM, where noise margin is a fundamental device control issue). An optimum, field-based OPC solution will address these differences without compromising the performance benefits of field-based methods. In this paper we describe and compare the manufacturing implementation of flash-based and field-based OPC at the 45nm and 32nm device nodes.