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Simulators and empirical profiling data are often used to understand how suitable a specific hardware architecture is for an application. However, simulators can be slow, and empirical profiling-based methods can only provide insights about the existing hardware on which the applications are executed. While the insights obtained in this way are valuable, they cannot be used to evaluate a large number of system designs efficiently.In this paper, we introduce an alternative to these approaches that is hardware-agnostic and enables fast designspace exploration. We propose a framework based on the LLVM compiler infrastructure that is capable of analyzing the inherent instruction-level parallelism and memory access patterns in sequential and parallel applications. The analysis is performed per thread or process during application execution. To illustrate the potential of the framework, we provide a detailed characterization of a representative benchmark for graph-based analytics, Graph 500. In addition to showcasing our tool's capabilities, our study complements previous Graph 500 characterization work by providing an analysis of the intrinsic properties of various implementations of the benchmark. Finally, we show how analytical models can leverage the software properties measured by our framework to enable fast system design-space exploration.

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