No abstract

In this paper, 28T CNFET-based full adder circuit is proposed. With the increase in the number of transistors and speed per unit chip area, power consumption of VLSI circuits has also increased. Power has become an extremely important design constraint along with the area and speed in modern VLSI design. So, carbon nanotubes with their superior properties, high current drivability, and high thermal conductivities have emerged as potential alternative devices to the CMOS technology. In this paper, average power consumption, energy and delay of Si MOSFET and CNFET-based full adder have been analyzed. The simulation was carried out using HSPICE circuit simulator. The simulation results show that power consumption, energy, and PDP of CNFET-based full adder is 56, 54.74, and 59 % reduced, respectively, in comparison to the Si MOSFET-based full adder. Moreover, the delay is also reduced approx by 8.69 % for sum output and 8.63 % for carry output.