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With transistors scaling towards sub 14nm nodes, FIN-field effect transistors (FINFETs) have been the preferred design architecture to meet device requirements. The gate last/replacement metal gate (RMG) integration scheme forms the core design for FINFETs due to the advantages in thermal budgets. Chemical Mechanical Planarization (CMP) plays a key role in this integration scheme with various CMP steps supporting dummy poly gate formation, poly removal and replacement metal gate formation. And the final gate height after metal gate CMP process typically determines device resistance. Therefore, one of major requirements of metal gate CMP is to control gate height as tightly as possible for every wafer. In this paper, two fold approaches are introduced to achieve this. Integrated advanced process control (iAPC) method improves wafer to wafer variation, and zonal iAPC provides additional within wafer variation improvement. The concept of iAPC is to use data collected from each wafer and to adjust polishing time (and zone pressure for zonal iAPC case) to achieve final gate height. Using these two approaches, gate height control of less than 5nm has been demonstrated.