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This paper presents several design issues of CMOS latch/flipflops for meta-stable hardness in terms of optimal device size, aspect ratio, and configurations by using the AC small signal analysis in the frequency domain rather than the time domain. This new design approach is verified experimentally. T h e power supply disturbance and temperature variation effects on the metastability are measured and the measurement data confirm that a reduced power supply voltage and a higher temperature cause a lower meta-stable resolving capability.

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