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A surface-illuminated photoconductive detector based on Ge 0.9 Sn 0.1 quantum wells with Ge barriers grown on a silicon substrate is demonstrated. Photodetection up to 2.2µm is achieved with a responsivity of 0.1 A/W for 5V bias. The spectral absorption characteristics are analyzed as a function of the GeSn/Ge heterostructure parameters. This work demonstrates that GeSn/Ge heterostructures can be used to developed SOI waveguide integrated photodetectors for short-wave infrared applications. 2012 Optical Society of America References and links1. J. Menendez and J. Kouvetakis "Type-I Ge/Ge1−x−ySixSny strained-layer hetero-structures with a direct Ge Bandgap", Applied Physics Letters, 85(7), 1175-1177 (2004). 2. G. Sun, R. A. Soref, H. H. Cheng, "Design of a Si-based lattice-matched room temperature GeSn/GeSiSn multiquantum-well mid-infrared laser diode", Optics Express 18(19), 19957-19965 (2010). 39(3), 1871-1883, (1989). 14. M. Krijn, "Heterojunction band offsets and effective masses in III-V quaternary alloys" Semiconductor Science and Technology, 6(1), 27-31 (1991

Strain relaxation in large lattice-mismatched epitaxial films, such as Ge and III-V materials on Si, introduces high threading dislocation densities ͑TDDs͒. A thermodynamic model of TDD dependence on film thickness is developed. According to this model, the quasiequilibrium TDD of a given strain-relaxed film scales down with the inverse square of its thickness. The quasiequilibrium TDDs in both Ge and GaAs films follow this model consistently. Our model predicts the lowest possible TDD of a large lattice-mismatched film on Si ͑100͒, which is determined by the dislocation glide activation energy and the film thickness.

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Further improving complementary metal oxide semiconductor performance beyond the 22 nm generation likely requires the use of high mobility channel materials, such as Ge for p-type metal oxide semiconductor (pMOS) and III/V for n-type metal oxide semiconductor devices. The complementary integration of both materials on Si substrates can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates using Si wafers with standard shallow trench isolation (STI). This reduces the fabrication cost of these virtual substrates as the complicated isolation scheme in blanket Ge can be omitted. The low topography enables integration of ultrathin high- k gate dielectrics. The fabrication schemes are also compatible with uniaxial stress techniques. Both modules include an annealing step at 850°C to reduce the threading dislocation densities down to 4×108 and 1×107cm−2 , respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter are illustrated by preliminary results of selective epitaxial InGaAs growth on virtual Ge substrates.