Abstract:The rising integration level enables combining more logic on a single chip. This is exploited in multiprocessor systems-on-chip (MPSoCs) or manycore research prototypes such as the Intel SCC. These platforms offer access to shared memory over a limited number of controllers which may lead to congestion. In order to scale the memory with the core count, the memory management must become more flexible and distributed in nature. In the near future decentralized systems with multiple selfmanaging memory components will arise.The problem tackled in this paper is how to realize synchronization mechanisms for coincident access to shared memory in such a decentralized memory management system. Furthermore, improvements of the distributed synchronization mechanism are integrated and evaluated. To speed up the synchronization, additional logic in the form of a locks queue, is added. In order to reduce the network traffic this is combined by extending the synchronization protocol with exponential backoff. In the evaluation, side effects of combining both techniques are discussed and explained.