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Abstract. In this paper we present a method to translate VHDL into symbolic finite-state models. Our method can handle those aspects of VHDL which have a finite representation obtaining the semantics defined in the IEEE statndard. We describe an intermediate representation based on finite automata and its translation into a BDD-based reperesentation. Our model interfaces VHDL with a BDD-based functional symbolic model checker.

We present a partitioning algorithm for checking ACTL specifications that distinguishes between states only if this is necessary to ascertain the specification. This algorithm is then generalized to also abstract from the variable values in the states. Here, too, the values between which the algorithm distinguishes are determined by what is needed to decide whether or not the specification holds. The resulting algorithm is being implemented in an ROBDD based model checker for VHDL/S.

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