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Pontificia Universidade Catolica do Rio Grande do Sul -PUCRS Av.1 piranga 6681, prCdio 30 sala 152 Porto Alegre -RS -B r a d ABSTRACTThis work proposes a speech recognition system based on a hardwarelsoftware co-design implementation approach. The main advantage in this approach is an expressive processing time reduction in speech recognition, because part of the system is implemented by dedicated hardware. This work also discuss another way to implement" Hidden Markov Models" (HMM), a probabilistic modele xtensively used in speech recognition systems. In thisn ew approach, the Viterbi algorithm, used to compute the H M M likelihood score, will be "built in" together with the H M M structure designed in Hardware, and implementing probabilistic state machines that will run as parallel processes each one for each word in the vocabulary handled by the system. So far, we have a dramatic speed up performance, getting meseaures around 500 times faster than a classic implementation with the correctnessc omparable with others isolated word recognition systems.' Professor in ElectricalD epartment, Engineering Schoola tP ontificia Universidade Catolica do Rio Grande do SUI, Porto Alegre - RS -Brazil

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3D NoC-based architectures have emerged to reduce the network latency, the energy consumption and total area in comparison to 2D NoC topologies. However, they are characterized by various trade-offs with regard to the three dimensional structure and its performance specifications. In this paper, we present a 3D NoC mesh architecture called Lasio, whose latency and the throughput achieved, for both network and application, are evaluated considering two types of traffic patterns, varied buffer depth and a range of packet sizes. Cycle-accurate simulations demonstrated that there is a high impact of buffer depth and packet size on the NoC latency and on the application latency. Applying an appropriate buffer depth, for several sizes of packets, the application latency is reduced and throughput is increased.