This paper introduces a design of gaussian Laplace edge detection algorithm model based on system generator which can be realized in FPGA.The data of a two- dimensional image was changed into a one-dimensional array，before line buffering in two Dual port RAM,the convolution of the image pixel data and the LOG template was carried out in the modules constituted of the component elements such as AddSub, Shift and Delay . After getting the absolute value with the modules of Slice，Negate and Mux ，the output was the image after edge-detection .The module function and the selecting principle was analyzed from the point of view of saving FPGA resources.The WaveScope and resource estimator showed that ：not only the detection result and the running speed was guaranteed but also the FPGA resources can be saved .

This paper discussed a conventional fast median filtering algorithm for FPGA implementation. An improved way -- Quasi-median filtering algorithm -- have been proposed to reduce the occupancy rate of FPGA resources on the premise of ensuring the result of median filtering. Through the detailed analysis and comparison of results of simulation and experiments, conclusions can be drawn that such improvements can achieve better filtering results, and can reduce FPGA resource utilization. It offers some value for the application of design which requires more FPGA resources.