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Assuming arbitrary (continuous cell sizes) we have achieved global minimization of the total transistor sizes needed to achieve a delay goal, thus minimizing dynamic power (and reducing leakage power). We then developed a feasible branchand-bound algorithm that maps the continuous sizes to the discrete sizes available in the standard cell library. Results show that a well-designed library gives results close to the optimal continuous size results. We developed a new approach to threshold voltage selection, among options available in a cell library. This algorithm is applied after optimal gate size selection, and raises threshold voltages as much as possible while strictly maintaining the delay goal. In addition, we identified the optimal set of (just 8) combinational functions in a physical cell library. These constitute the most power efficient cells needed to implement combinational logic. On the other hand, the synthesis library is much more complex, consisting of cells that are combinations of the physical library cells. This is advantageous since the constituent cells (of a more complex synthesis cell) are placed next to each other in the layout, ensuring minimal wire length between them. Since wire delay is a significant portion of total path delay for contemporary circuits, having complex cells in synthesis is important. But, for power efficiency, the physical cells must be rather simple, with no more than two transistors in series for any cell. The entire cell size and threshold voltage selection flow is efficient, with an ability to handle multi-million-gate commercial designs. After using state-of-the-art commercial synthesis, the application of our design automation tools and library results in a dynamic power reduction of 25-35% and leakage power reduction by 50-70% for large logic blocks.

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