We report that a Ni–InGaAs alloy can be used as a source/drain (S/D) metal for InGaAs metal–oxide–semiconductor field-effect transistors (MOSFETs), allowing us to employ the salicide-like self-align S/D formation. We also introduce Schottky barrier height (SBH) engineering process by increasing the indium content of InxGa1-xAs channels, which successfully reduces SBH down to zero. We propose a fabrication process for self-aligned metal S/D MOSFETs using Ni–InGaAs and demonstrate successful operation of the metal S/D InxGa1-xAs MOSFETs. The In0.7Ga0.3As MOSFETs exhibit an S/D resistance (RSD) that is 1/5 lower than that in P–N junction devices and a high peak mobility of 2000 cm2 V-1 s-1.

No abstract

We have demonstrated extremely-thin-body (ETB) (3.5 and 9 nm) InGaAs-on-insulator (InGaAs-OI) MOSFETs on Si substrates with Al 2 O 3 ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding (DWB). We have found that the ETB highly-doped InGaAs-OI n-channel MOSFETs without p-n junction can perform a normal MOSFET operation under front-and back-gate configuration and the double-gate operation can provide excellent on-current/offcurrent (I on /I off ) properties of ~10 7 and the improved S factor even for InGaAs-OI MOSFETs with N D of 1×10 19 cm -3 . InstructionIII-V semiconductors are promising candidates as channel materials for future CMOS transistors because of their high electron mobility and low effective mass [1]. We have developed III-V-On-Insulator (III-V-OI) structures with Al 2 O 3 BOX layers using DWB and have demonstrated the In 0.53 Ga 0.47 As-OI MOSFETs (InGaAs body thickness, d InGaAs > 20 nm) on Si with the high electron mobility [2]. In order to apply this device to future technology node CMOS with short gate length L G , the III-V-OI-on-Si structures with ETB less than 10 nm are mandatory. However, the demonstration of III-V-OI MOSFETs with such thin bodies and any analyses of the electrical characteristics have not been reported yet. One of the most critical issues in realizing ETB III-V-OI MOSFETs is the source/drain (S/D) junction formation in ETB III-V-OI films. In order to solve this problem, we newly introduce n-doped accumulation-mode channels without pn junctions [3] to ETB III-V-OI structures fabricated by DWB. This device structure allows us to fabricate MOSFETs without using ion implantation and high temperature activation annealing, which are quite difficult in applying to ETB III-V-OI channels.As a result, we demonstrate, for the first time, the operation of ETB and UTBOX InGaAs-OI n-channel MOSFETs, where the channel thickness is reduced down to 3.5 nm. It is found that the double-gate operation through Al 2 O 3 gate insulators and UTBOXs can yield superior MOSFET performance with high I on /I off ratio of ~10 7 even in the 9-nm-thick InGaAs-OI devices with the doping concentration N D of 1×10 19 cm -3 . We also clarify that the surface roughness plays an import role for the mobility degradation in the ETB III-V-OI MOSFETs with the body thickness less than 10 nm. Simulation and fabrication of n-doped ETB InGaAs-OI MOSFETsThe present ETB InGaAs-OI structure is shown in Fig. 1. Here, the III-V-OI channel regions including S/D are highly doped with n-type impurities and, thus, the MOSFETs have no p-n junctions. Recently, the device operation of Si nanowire MOSFETs with this channel structure has been demonstrated on SOI substrates [3]. In order to examine the applicability of this structure to InGaAs-OI channels, we examine the device characteristics and the device parameter dependence by using device stimulation (Sentaurus).We calculated the device performance of the highly-doped ETB InGaAs-OI MOSFETs. It was assumed here that the work function of a front-gate Ni is 5.1...

No abstract