The Charles Stark Draper Laboratory, under contract to the NASA Johnson Space Center, has developed a Fault-Tolerant Parallel Processor (FTPP) for use on the NASA X-38 experimental vehicle. Using commercial processor boards and the industry-standard VME backplane, the system is configured as a quadruplet Flight-Critical Processor (FCP) and five simplex Instrumentation Control Processors (ICPs). The FCP is Byzantine resilient for any two non-simultaneous permanent faults, and for any number of non-simultaneous recoverable faults, as long as a maximum of one other fault condition occurs during the recovery process (only two recoveries can be in progress at once).To obtain Byzantine resilience, there are a number of constraints on the design of a redundant system. First, the redundant channels must be electrically isolated. Second, the redundancy level is a function of the number of simultaneous faults and the total number of permanent faults to be tolerated. Third, there must be a voting mechanism that finds and communicates errors to the system. Fourth, there must be synchrony (to some accuracy) among the redundant channels. For the X-38 FTPP, the first three of these are implemented solely in hardware. The timing constraints are implemented both in hardware and in sohare. This paper will focus on some of the hardware and software design of the Fault-Tolerant System Services (FTSS) that isolate, as much as possible, the redundancy of the FCP from the application sohare, such as the guidance, navigation and flight control software, on the X-38 FTPP. FTSS also performs reconfiguration and recovery functions.were found to be necessary based on the use of current COTS processor boards. For example, maintaining consistent timing across multiple channels, while using cache memory, will be described.There are certain constraints on the design that There are constraints on the application due also to the need to maintain consistent timing. To avoid even more constraints on the application, the FTSS needs information about the application to handle certain failures. These will also be described.

Failure analysis is important in determining root cause for appropriate corrective action. In order to perform failure analysis of microelectronic application-specific integrated circuits (ASICs) delidding the device is often required. However, determining root cause from the front side is not always possible due to shadowing effects caused by the ASIC metal interconnects. Therefore, back-side polishing is used to reveal an unobstructed view of the ASIC silicon transistors. This paper details how back-side polishing in conjunction with laser-scanned imaging (LSI), laser voltage imaging (LVI), laser voltage probing (LVP), photon emission microscopy (PEM), and laser-assisted device alterations (LADA) were used to uncover the root cause of failure of two ASICs.