A single-chip GPS receiver for GSM and CDMA handsets, designed to provide location identification feature, is described in this paper. This receiver uses a low-IF RF-front-end, that includes an LNA, image rejection using IQ mixers and passive poly-phase filter, and a fully integrated synthesizer. The IF-strip consists of a jammer-reject filter, a VGA, delta-sigma ADC and a digital IF-filter. An attempt is made to minimize the number of external components and have only a single pre-select filter between the antenna and the IC. In the absence of any SAW filter, the ability of the receiver to tolerate jammers is very critical, due to the vicinity of the transmitter of the handset. The receiver works in the GPS L-1 band at 1575.42MHz, which carries the C/A code.Recently, there has been an increased level of interest in GPS receivers [1][2][3]. A very low-power CMOS implementation, that uses a 2b quantizer and external loop-filters for its synthesizer and AGC, is reported in [2]. The receiver discussed in [4] uses a SAW filter for the IF filtering and an external loop-filter for the synthesizer.This chip uses an IF of 4.092MHz. Direct conversion and low-IF are the most popular wireless receiver architectures today. Direct conversion avoids the problem of image frequency, but issues associated with low-frequency noise, DC offset and LO-leakage make its implementation extremely difficult. Frequency planning of the proposed receiver is chosen to keep the reference clock harmonics and any wireless transmissions far away from the signal and image bands. Hence the primary requirement on image rejection is to reject the thermal noise in the image-band, and a relatively low image-rejection of 15dB can preserve the in-band SNR. A pre-select filter is required to keep the out-of-band signals from blocking the receiver. The block diagram of the receiver is shown in Fig. 17.1.1. The receiver uses no off-chip component, other than a crystal for reference clock and supply-decoupling capacitors. Except for the LNA, the entire receiver uses differential signal processing to improve immunity to supply and substrate disturbances.The LNA has single-ended input and differential output. Pinout is selected to isolate the RF signals from other package coupling. LNA uses tuned load designed with spiral inductors for improved linearity and NF. The LNA output is applied to two double-balanced mixers through capacitors used for AC coupling and matching. These two mixers perform down-conversion using I and Q components of LO. Subsequently, the IF-chain performs filtering and further amplification. The linearity of GPS signal in the presence of cellular-band jammers is one of the key performance parameters of this front-end.The first block in the IF-chain is a second-order regulated cascode stage. This filter rejects the out-of-band jammers, that are at least 140MHz away from GPS band. This block also provides lownoise amplification of the IF signal. The amplification in this stage comes from ratio of resistors and hence the required IQ balance ...

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This paper presents a highly integrated, high performance four channel linear transimpedance amplifier (TIA) RFIC with a footprint of 2mmx3.5mm towards next generation 100G/400G miniaturized coherent receivers. A TIA of such form may become indispensable as the size, complexity and cost of receivers continue to reduce. The design has been realized in a 130nm SiGe BiCMOS process for a low cost, high performance solution towards longhaul/metro applications. The TIA is capable of providing control functions either digitally through an on-chip 4-wire serial-peripheral interface (SPI) or in analog mode. Analog mode is provided as an alternative control for real-time control and monitoring. To provide high input dynamic range, a variable gain control block is integrated for each channel, which can be used in automatic or manual mode. The TIA has a differential input, differential output configuration that exhibits state-of-the-art THD of <0.9% up to 500mVpp output voltage swing for input currents up to 2mApp and high isolation > 40dB between adjacent channels. A high transimpedance gain (Zt) up to ~7KΩ with a large dynamic range up to 37dB and variable bandwidth up to 34GHz together with low average input noise density of 20pA/√Hz has been achieved. To the authors' knowledge, these metrics combined with diverse functionality and high integration have not been exhibited so far. This paper intends to report a state-of-the-art high-baud rate TIA and provide insight into possibilities for further integration.

We propose a 100 GHz sub-harmonic injection locked oscillator (ILO) based Phase-Locked Loop (PLL) in CMOS for use in low power Millimeter-Wave (mm-Wave) and sub-Terahertz (THz) phased-array systems. PLL parameters for an imaging system are derived. Mixed-mode simulation to enhance simulation speed has been done with custom Verilog-A models for the PFD/CP/divider and circuit schematic of the ILO. PLL with a 2 nd sub-harmonic ILO at 101 GHz driving a 50 Ω load is shown. Simulated using 1.1 V supply, the PLL phase noise is -76.5 dBc/Hz @ 1 MHz offset, frequency tuning range of ILO is 7 GHz, output power is -9.1 dBm at the load, and power consumption is 14.4 mW. The circuits are implemented in standard digital 65 nm CMOS, enabling high level of on-chip integration.

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