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We report on spectroscopy of a single dopant atom in silicon by resonant tunneling between source and drain of a gated nanowire etched from silicon on insulator. The electronic states of this dopant isolated in the channel appear as resonances in the low temperature conductance at energies below the conduction band edge. We observe the two possible charge states successively occupied by spin-up and spin-down electrons under magnetic field. The first resonance is consistent with the binding energy of the neutral D 0 state of an arsenic donor. The second resonance shows a reduced charging energy due to the electrostatic coupling of the charged D ÿ state with electrodes. Excited states and Zeeman splitting under magnetic field present large energies potentially useful to build atomic scale devices. DOI: 10.1103/PhysRevLett.97.206805 PACS numbers: 73.21.ÿb, 61.72.Vv Dopant atoms are essential in semiconductor technology since they provide extrinsic charges necessary to create devices such as diodes and transistors. Nowadays the size of these electronic devices can be made so small than the discreteness of doping can influence their electrical properties [1]. On the other hand, it may be an important breakthrough if a dopant could be used as the functional part of a device instead of just providing charges. As an example, dopant-based spin qubits in silicon are possible candidates for quantum computation [2,3] thanks to their longer spin coherence time [4] as compared to twodimensional quantum dots defined by top gates in III=V heterostructures [5,6]. Although dopants are well known in bulk semiconductors, specific questions arise in the context of nanoscale devices like the reduced lifetime of the twoelectron state under electric field involved by readout schemes of spin qubits [7]. The aim of this work is to study the electronic states of single dopants in gated silicon nanostructures to bring information useful for these issues.Electron tunneling through isolated impurities has been observed previously in two-terminal devices such as GaAs= Al; Ga As double barrier heterostructures [8,9]. Here we present experimental results on electron transport through the localized states of individual n-type dopants in silicon nanowires. In contrast to previous studies, our devices have a three-terminal configuration with source, drain, and gate electrodes allowing a detailed investigation of charge, orbital, and spin states. In particular, we observe both the neutral D 0 and negatively charged D ÿ states, and compare their binding energy with the case of bulk dopants. This work provides a quantitative description of the electronic properties of a single dopant connected to electrodes in a gated nanostructure. This is the first transport experiment measuring the charge states of a real atomic system with a 1=r attracting Coulomb potential, thus very different from quantum dots with harmonic potentials.Our devices are 60 nm tall crystalline silicon wires (fins) with large contacts patterned by 193 nm optical lithography and ...

Articles you may be interested inDetailed leakage current analysis of metal-insulator-metal capacitors with ZrO2, ZrO2/SiO2/ZrO2, and ZrO2/Al2O3/ZrO2 as dielectric and TiN electrodes J. Vac. Sci. Technol. B 31, 01A109 (2013); 10.1116/1.4768791 Impact of bottom electrode and Sr x Ti y O z film formation on physical and electrical properties of metalinsulator-metal capacitors Appl. Phys. Lett. 98, 182902 (2011); 10.1063/1.3584022 Influence of precursor chemistry and growth temperature on the electrical properties of SrTiO 3 -based metalinsulator-metal capacitors grown by atomic layer deposition J. Vac. Sci. Technol. B 29, 01AC04 (2011); 10.1116/1.3525280 Impact of crystallization behavior of Sr x Ti y O z films on electrical properties of metal-insulator-metal capacitors with TiN electrodes Appl. Phys. Lett. 97, 162906 (2010); 10.1063/1.3505323 Atomic-layer-deposited Al 2 O 3 -Hf O 2 -Al 2 O 3 dielectrics for metal-insulator-metal capacitor applications Appl. Phys. Lett.In this work, the physical and electrical properties of Sr x Ti 1−x O y ͑STO͒-based metal-insulator-metal capacitors ͑MIMcaps͒ with various compositions are studied in detail. While most recent studies on STO were done on noblelike metal electrodes ͑Ru, Pt͒, this work focuses on a low temperature ͑250°C͒ atomic layer deposition ͑ALD͒ process, using an alternative precursor set and carefully optimized processing conditions, enabling the use of low-cost, manufacturable-friendly TiN electrodes. Physical analyses show that the film crystallization temperature, its texture and morphology strongly depends on the Sr/Ti ratio. Such physical variations have a direct impact on the electric properties of Sr x Ti 1−x O y based capacitors. It is found that Sr-enrichment result in a monotonous decrease in the dielectric constant and leakage current as predicted by ab initio calculations. The intercept of the EOT vs physical thickness plot further indicates that increasing the Sr-content at the film interface with the bottom TiN would result in lower interfacial equivalent-oxide thickness.

The Kondo effect has been observed in a single gate-tunable atom. The measurement device consists of a single As dopant incorporated in a silicon nanostructure. The atomic orbitals of the dopant are tunable by the gate electric field. When they are tuned such that the ground state of the atomic system becomes a (nearly) degenerate superposition of two of the silicon valleys, an exotic and hitherto unobserved valley Kondo effect appears. Together with the "regular" spin Kondo, the tunable valley Kondo effect allows for reversible electrical control over the symmetry of the Kondo ground state from an SU(2) to an SU(4) configuration.

The authors investigate the subthreshold behavior of triple-gate silicon field-effect transistors by low-temperature transport experiments. These three-dimensional nanoscale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers down to 50ϫ 60ϫ 35 nm 3 . Conductance versus gate voltage shows Coulomb blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analyses, the authors conclude that subthreshold channels, a few nanometers wide, appear at the nanowire edges, hence providing an experimental evidence for the corner effect. © 2007 American Institute of Physics. ͓DOI: 10.1063/1.2476343͔ Nonplanar field-effect transistors called FinFETs ͑Ref. 1͒ are currently being developed to solve the problematic issues encountered with the standard planar geometry when the channel length is reduced to a sub-100 nm size. Their triplegate geometry is expected to have a more efficient gate action and to solve the leakage problem through the body of the transistor, one of the dramatic short channel effects. 2 However, their truly three-dimensional ͑3D͒ structure makes doping-and thus also potential-profiles very difficult to simulate and to understand using the current knowledge on device technology. Transport studies at low temperature, where the thermally activated transport is suppressed, can bring insight to these questions by measuring local gate action. For this reason we experimentally investigate the potential profile by conductance measurements and observe the formation of a subthreshold channel at the edge of the silicon nanowire. This corner effect has been proposed 3,4 as an additional contribution to the subthreshold current in these 3D triple-gate structures, where the edges of the nanowire experience stronger gate action due to the geometric enhancement of the field. However, besides extensive simulation work 3,4 -keeping in mind the difficulties with these 3D structures-very little experimental work has been published until now on this effect. 5 The FinFETs discussed here consist of a narrow singlecrystalline silicon wire with two large contact pads etched in a p-type silicon on insulator layer doped with 10 18 cm −3 boron atoms. This silicon wire is covered with a t ox = 1.4 nm thick thermal oxide and a second narrow polycrystalline silicon wire crossing the first one is fabricated to form a gate that surrounds the wire on three faces ͓Fig. 1͑a͔͒. The entire surface is then implanted with 10 19 cm −3 arsenic atoms to form n-type degenerate source, drain, and gate. During this implantation the wire located below the gate is protected and remains p type. In the investigated device series the height of the fin wire is H = 60 nm, while the width ranges from W =35 nm to 1 m and the gate length ranges from L =50 nm to 1 m. The relatively high p-type doping of the channel wire is chosen to ensure a depletion...