After encapsulation, thermomechanical deformation builds up within the electronic packages due to the temperature coefficient of expansion mismatch between the respective materials within the package as it cools to room temperature. At the same time, the chemical cure shrinkage exerts important influence on the total deformation. Due to the complexity and time consuming of the calculation, it is almost impossible for an industry to carry out the numerical simulation using viscoelastic property, which is the most close to the real material property of polymer material. However, finite element analysis (FEA) using temperature-dependent elastic property, temperature-dependent thermal expansion coefficient, and accurate chemical cure shrinkage can help to improve the accuracy on the stress and warpage prediction. This study has developed an evaluation method for the chemical cure shrinkage based on the measurement of the warpage of bimaterial model. The results show that FEA simulations without chemical cure shrinkage fail to accurately predict the package warpage. On the other hand, FEA simulations with chemical cure shrinkage are outlined, which show fair agreement with experimental measurements of package warpage over a range of temperatures. Furthermore, this study has evaluated the effect of silica filler percentage on the chemical cure shrinkage and confirmed that the chemical cure shrinkage decreases with the increase in silica filler percentage.
The 3 D interconnect technology with Thru Silicon Via (TSV) have gained tremendous advancement in recent years. Final adoption of TSV technologies requires a robust and cost competitive TSV processes. Sidewall plated TSV with polymer filling can reduce half of total process steps from TSV copper (Cu) seed deposition to front-via1 expose. TSV plating time can be reduced ~ 60% for sidewall plated TSV with polymer filling. Costly Cu removal process through chemical mechanical polishing (CMP) can be skipped in sidewall plated TSV with polymer filling process. Wafer warpage and bow for sidewall plated TSV with polymer filling were shown to be ~70% and ~94%, respectively lower than solid Cu filled TSV. Thermal-mechanical simulation show 20% and 42% reduction of shear and bending stress respectively in the case of sidewall plated TSV with polymer filling. IntroductionThe concept of 3D packaging using TSV stacking is one of the most promising technologies. It can extend Moore's Law by stacking and shortening the connection path between memory and logic [2]. Due to the increased in functional integration requirements, more and more assembly house and wafer foundries are looking into 3D TSV technology, which allows stacking of Large Scale Integrated Circuits (LSIs) thereby enabling products to be made smaller with more functionality. 3D technology realizes miniaturization by 300-400% compared to the conventional packaging [3].Although the electrical benefits are greatly increasing in stacked IC packages, their corresponding thermo-mechanical problems are raising as well. This includes problem of coefficient of thermal expansion (CTE) mismatch between copper (~17.5x10 -6 / o C) and silicon (~2.5x10 -6 / o C), heat dissipation, induced stresses, interfacial delimitation, via cracking and so on [1,4,5,6]. Wafer warpage and stress is one of challenge within TSV process integration. Local TSV stress directly decides the TSV performance and reliability. We will focus on wafer warpage and stress comparison for the solid and sidewall plated TSV with polymer filling in this paper. Simulation results were used for the comparison of the local stress in two different approaches.
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