Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dryetching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology.

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