MechanicaI reliability is widely recognized as the primary obstacle to productization of porous low-k materials. The combination of weak bulk and interfacial properties with increasingly complex geometries poses a considerable challenge at the 65-nm node. The final solution must be sufficiently robust so as to ensure compatibility with multiple substrate types, interconnect configurations and packages. In this work, material engineering, modeling, design rule tailoring, and assembly optimization are employed to achieve required assembly reliability for both wirebond and flip-chip packages, for both bulk and SO1 substrates.

Amongst solutions to connect the die to the package, thermosonic wire bonding process remains widely used. However, the introduction of low-k dielectric materials, and the feature size decrease of IC chips to follow Moore's law, pose great integration challenge.This paper aims to demonstrate the compliance of the proposed modeling approach with the aids of experimental validations. 3D multi scale simulation of both bonding process and wire pull test is carried out. Using a previously validated homogenization procedure to include pad structure description even at the global scale, stress fields acting in the copper/low-k stack are evaluated. The modeling strategy also includes an in-house developed energy based analysis.For the experimental part, a wide range of wire bond trials have been performed in order to qualify the 65-nm technology node. On behalf of that, several bond pad architectures have been implemented and wire bonded on a test vehicle. It was found a significant effect of the copper/low-k design on peeling failure rates, in particular with severe bonding conditions. In this paper, typical modeling results are presented. Contrary to stress based one, the energy based analysis shows a better ability to forecast the observed failed interface. From simulation results obtained, it is confirmed that the bonding process plays major role in the peeling failure, despite the fact that most of them are observed during the wire pull test. Failure mechanisms are also proposed. Then, the implemented pad structures are evaluated and analyzed. Both general trends and architecture ranking are provided. Simulations are then faced to experimental results and a full agreement is found. The complementary nature of the energy based failure criteria is again highlighted through a clearer discrimination of the tested structures.Finally, the simulation procedure with confirmed experimental results demonstrates its ability in design and process optimizations by providing a better understanding of pad peeling failure mechanisms.

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Experience has shown that in thin packages ( 2 0~2 0~1 . 4 mm), molding defects occur somewhat more frequently with large devices (12.7x12.7 mm), and devices molded in the die-down configuration. For these unique conditions, the mold compound flow front advanced slowly over the top surface of the die and rapidly over the back of the die exposed by the X-flag l e a d m e design. The most frequent defect observed in evaluations of die-up and diedown molding was exposed silicon after molding, caused by the uneven mold compound flow.To develop a robust molding process window, designed experiments were used to evaluate leadframe downset, mold gate design, molding compound, and molding parameters. Results showed that the leadframe downset was the most significant variable to improve moldability, and a deeper downset produced the best results. The molding process was optimized with two molding compounds, and the manufacturing process window is robust over a large variety of device sizes in both die-up and die-down molding configurations. All

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