No abstract

No abstract

No abstract

Abstract. An ESD failure occurring inside the core circuitry known as “inverter failure" will be presented and analysed in this paper. The compact model utilised for this investigation is shortly presented. It will be shown that not only properties of the failed structure are relevant, but also surrounding circuitry. So the gate of an inverter will be connected during the simulations in diverse ways to VDD and VSS. The different possibilities of influence of pre drivers can be appraised in this way. In order to achieve a detailed understanding of the individual failure, it is necessary to include ambient circuitry as well as parasitics like resistors and capacitances.

A multi-terminal TLP measurement technique is used for accessing current and voltage distributions during ESD in typical I/O cell frames in a 0.13um CMOS technology. The procedure extends traditional I/O library testchip based ESD verification and qualification tests, allows to calibrate ESD chip-level simulation tools and to derive precise I/O library application rules.