Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.

Oxide-semiconductor interface quality of high-pressure reactive sputtered (HPRS) TiO 2 films annealed in O 2 at temperatures ranging from 600 to 900 • C, and atomic layer deposited (ALD) TiO 2 films grown at 225 or 275 • C from TiCl 4 or Ti(OC 2 H 5 ) 4 , and annealed at 750 • C in O 2 , has been studied on silicon substrates. Our attention has been focused on the interfacial state and disordered-induced gap state densities. From our results, HPRS films annealed at 900 • C in oxygen atmosphere exhibit the best characteristics, with D it density being the lowest value measured in this work (5-6 × 10 11 cm −2 eV −1 ), and undetectable conductance transients within our experimental limits. This result can be due to two contributions: the increase of the SiO 2 film thickness and the crystallinity, since in the films annealed at 900 • C rutile is the dominant crystalline phase, as revealed by transmission electron microscopy and infrared spectroscopy. In the case of annealing in the range of 600-800 • C, anatase and rutile phases coexist. Disorder-induced gap state (DIGS) density is greater for 700 • C annealed HPRS films than for 750 • C annealed ALD TiO 2 films, whereas 800 • C annealing offers DIGS density values similar to ALD cases. For ALD films, the studies clearly reveal the dependence of trap densities on the chemical route used.

We have analyzed the electrical properties and bonding characteristics of SiNx:H thin films deposited at 200 °C by the electron cyclotron resonance plasma method. The films show the presence of hydrogen bonded to silicon (at the films with the ratio N/Si&lt;1.33) or to nitrogen (for films where the ratio N/Si is higher than 1.33). In the films with the N/Si ratio of 1.38, the hydrogen content is 6 at. %. For compositions which are comprised of between N/Si=1.1 and 1.4, hydrogen concentration remains below 10 at. %. The films with N/Si=1.38 exhibited the better values of the electrical properties (resistivity, 6×1013 Ω cm; and electric breakdown field, 3 MV/cm). We have used these films to make metal-insulator-semiconductor (MIS) devices on n-type silicon wafers. C–V measurements accomplished on the structures indicate that the interface trap density is kept in the range (3–5)×1011 cm−2 eV−1 for films with the N/Si ratio below 1.38. For films where the N/Si ratio is higher than 1.4, the trap density suddenly increases, following the same trend of the concentration of N–H bonds in the SiNx:H films. The results are explained on the basis of the model recently reported by Lucovsky [J. Vac. Sci. Technol. B 14, 2832 (1996)] for the electrical behavior of (oxide–nitride–oxide)/Si structures. The model is additionally supported by deep level transient spectroscopy measurements, that show the presence of silicon dangling bonds at the insulator/semiconductor interface (the so-called PbN0 center). The concentration of these centers follows the same trend with the film composition of the interface trap density and, as a consequence, with the concentration of N–H bonds. This result further supports the N–H bonds located at the insulator/semiconductor interface which act as a precursor site to the defect generation of the type •Si≡Si3, i.e., the PbN0 centers. A close relation between interface trap density, PbN0 centers and N–H bond density is established.

An electrical characterization of Al2O3 based metal-insulator-semiconductor structures has been carried out by using capacitance-voltage, deep level transient spectroscopy, and conductance-transient (G-t) techniques. Dielectric films were atomic layer deposited (ALD) at temperatures ranging from 300 to 800 °C directly on silicon substrates and on an Al2O3 buffer layer that was grown in the same process by using 15 ALD cycles at 300 °C. As for single growth temperatures, 300 °C leads to the lowest density of states distributed away from the interface to the insulator [disorder-induced gap states (DIGS)], but to the highest interfacial state density (Dit). However, by using 300∕500°C double growth temperatures it is possible to maintain low DIGS values and to improve the interface quality in terms of Dit. The very first ALD cycles define the dielectric properties very near to the dielectric-semiconductor interface, and growing an upper layer at higher ALD temperature produces some annealing of interfacial states, thus improving the interface quality. Also, samples in which the only layer or the upper one was grown at the highest temperature (800 °C) show the poorest results both in terms of Dit and DIGS, so using very high temperatures yield defective dielectric films.

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